1. Field
Exemplary embodiments of the present invention relate to a memory device.
2. Description of the Related Art
Memory devices such as DRAM have numerous memory cells, and as integration increases, the number of memory cells also increases. Such memory cells are regularly arranged to form a memory cell array.
The structure of memory devices can be classified into a folded bit line structure and an open bit line structure, and these structures have the following differences.
A bit line sense amplifier amplifies a voltage difference between a driving bit line, by which data is driven, and a reference bit line serving as a reference. In the folded bit line structure, the driving bit line and the reference bit line are arranged in substantially the same cell array. In the folded bit line structure, since the driving bit line and the reference bit line are arranged in the same cell array, the same noise is reflected on both the driving bit line and the reference bit line and these noises cancel each other. Through such cancellation, the folded bit line structure is robust to noise. In an open bit line structure, the driving bit line and the reference bit line are in different cell arrays. Accordingly, since noise generated in the driving bit line and the reference bit line is likely different, the open bit line structure is vulnerable to noise compared with the folded bit line structure.
However, the open bit line structure is advantageous in terms how much area it utilizes as compared with the folded bit line structure. In the folded bit line structure, the area of a unit memory cell may be designed to 8 F2, but in the open bit line structure, the area of a unit memory cell may be designed to 6 F2. The area of the unit memory cell is the most important factor in deciding the size (the area) of a memory device. A memory device having the open bit line structure may be designed smaller than a memory device having the folded bit line structure, assuming constant data storage capacity. Since the size (the area) of a memory device is the largest contributor to fabrication cost, most memory devices are designed using the open bit line structure.
FIG. 1 is a configuration diagram of conventional memory device having the open bit line structure.
Referring to FIG. 1, the memory device includes first to third cell arrays 111 to 113, a first sense amplifier array 121, a second sense amplifier array 122, and word line drivers 131 to 136.
Each of the first to third cell arrays 111 to 113 includes a plurality of word lines WL and a plurality of bit lines BL, and includes memory cells at intersection points between the word lines WL and the bit lines BL. The word line drivers 131 to 136 drive the word lines WL of the first to third cell arrays 111 to 113.
The first sense amplifier array 121 includes a plurality of sense amplifiers S/A. Each of the sense amplifiers S/A amplifies a voltage difference between each bit line BL of the first cell array 111 and each bit line BL of the second cell array 112. When the bit line BL of the first cell array 111 is the driving bit line, the bit line BL of the second cell array 112 is the reference bit line. When the bit line BL of the second cell array 112 is the driving bit line, the bit line BL of the first cell array 111 is the reference bit line.
The second sense amplifier array 122 includes a plurality of sense amplifiers S/A, wherein each of the sense amplifiers S/A amplifies a voltage difference between each bit line BL of the second cell array 112 and each bit line BL of the third cell array 113. When the bit line BL of the second cell array 112 is the driving bit line, the bit line BL of the third cell array 113 is the reference bit line. When the bit line BL of the third cell array 113 is the driving bit line, the bit line BL of the second cell array 112 is the reference bit line.
Bit lines BL of the first cell array 111, which are not coupled to the first sense amplifier array 121, and bit lines BL of the third cell array 113, which are not coupled to the second sense amplifier array 122, are not used because they are not amplified by sense amplifiers S/A of the first and second sense amplifier arrays 121 and 122. Even when additional sense amplifier arrays are disposed at an upper end of the first cell array 111 and a lower end of the third cell array 113 to be coupled to the un-coupled bit lines BL of the first and third cell arrays 111 and 113, since there are no reference bit lines for the un-coupled bit lines BL, it is still not possible to use these un-coupled bit lines.